The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (PET) are commonly named source, gate and drain. In the FET a small amount of voltage is applied to the gate in order to control current flowing between the source and drain. In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate, and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor. The space between the two diffusion areas is the “channel”. A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a “gate” structure is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Electrical connections (not shown) may be made to the source, the drain, and the gate. The substrate may be grounded.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in FIG. 2, the floating gate transistor 200 has a source and a drain, but rather than having only one gate, it has two gates which are called control gate (CG) and floating gate (FG). It is this arrangement of control gate and floating gate which enables the floating gate transistor to function as a memory cell, as described hereinbelow.
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a “conductor”).
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary “1”. If no charge is stored on the floating gate, this represents a binary “0”. (These designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single “charge-storing area”—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary “1” or binary “0”). More recently, using a technology referred to as “multi-level cell” (MLC), two or more bits can be stored in and read from the floating gate cell.
The NROM Memory Cell
Another type of memory cell, called a “nitride, read only memory” (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being flee to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary “1” or binary “0”) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary “1” or binary “0”) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage.
Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
FIG. 3 illustrates a basic NROM memory cell, which may be viewed as an FET with an “ONO” structure inserted between the gate and the substrate. (One might say that the ONO structure is “substituted” for the gate oxide of the FET.)
The ONO structure is a stack (or “sandwich”) of bottom (lower) oxide 322, a charge-trapping material such as nitride 324, and a top (upper) oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:                the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;        the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and        the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.        
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate between the two diffusion regions 314 and 316.
In FIG. 3, the diffusions are labeled “N+”. This means that they are regions in the substrate that have been doped with an electron donor material, such as phosphorous or arsenic. These diffusions are typically created in a larger region which is p-type cell well (CW) is doped with boron (or indium or both). This is the normal “polarity” for a NVM cell employing electron injection (but which may also employ hole injection, such as for erase). With opposite polarity (boron or indium implants in a n-type cell well), the primary injection mechanism would be for holes, which is generally accepted to be not as effective as electron injection. One skilled in the art will recognize that the concepts disclosed herein can be applied to opposite polarity devices.
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
The memory cell 300 is generally capable of storing at least two bits of data—at least one bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 321. Thus, the NROM memory cell can be considered to comprise two “half cells”, each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term “half cell”, as it may be used herein, is used herein only to refer to the “left” or “right” bit storage area of the ONO stack (nitride layer). The storage areas 321, 323 may variously be referred to as “charge storage areas”, “charge trapping areas”, and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left “bits”.)
Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (FIG. 2).
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary “1”, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary “0”. (Again, these designations are arbitrary, and can be reversed to that the charged state represents binary “0” and the discharged state represents binary “1”,) That represents the programming “half” of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is.
Generally, one feature of NROM cells is that rather than performing “symmetrical” programming and reading, NROM cells are beneficially programmed and read “asymmetrically”, which means that programming and reading occur in opposite directions. The arrows labeled in FIG. 3 are arranged to illustrate this point. Programming may be performed in what is termed the “forward” direction and reading may be performed in what is termed the “opposite” or “reverse” direction.
“Reading” an NROM Cell
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing “symmetrical” programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read “asymmetrically”, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in FIG. 3. Programming is performed in what is termed the forward direction and reading is performed in what is termed the opposite or reverse direction. For example, generally, to program the right storage area 323 (in other words, to program the right “bit”), electrons flow from left (source) to right (drain). To read the right storage area 323 (in other words, to read the right “bit”), voltages are applied to cause electrons to flow from right to left, in the opposite or reverse direction. For example, generally, to program the left storage area 321 (in other words, to program the left “bit”.), electrons flow from right (source) to left (drain). To read the left storage area 321 (in other words, to read the left “bit”), voltages are applied to cause electrons to flow from left to right, in the opposite or reverse direction. See, for example, U.S. Pat. No. 6,768,165.
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bitlines may be “buried bitline” diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
FIG. 4 illustrates an array of NROM memory cells (labeled “a” through “i”) connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell “e” has its gate connected to WL(n), its source (left hand diffusion) is connected to BL(n), and its drain (right hand diffusion) is connected to BL(n+1). The nine memory cells illustrated in FIG. 4 are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL(n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”. In this example, the memory cells “e” and “f” have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
Secondary Injection, and Managing Far From Junction Injection
Generally, NVM cells (both floating gate and ONO-based) are programmed by injecting electrons into the charge storage medium, such as the conductive floating gate of a floating gate memory cell, or the bit storage areas of the charge trapping layer (typically nitride) of an ONO-based memory cell.
A common mechanism for injecting electrons is channel hot electron (CHE) injection. Generally, in order to implement CHE injection of electrons into the charge storage medium, the source may be grounded, the drain may be set to a positive voltage (which will “attract” electrons from the source, laterally across the channel region), and the gate is also set to a positive voltage (which will “attract” electrons vertically through the tunnel oxide or bottom oxide of the ONO, into the charge storage medium). As electrons flow through the channel from source to drain, some of the electrons will make their way through the tunnel oxide (of floating gate) or bottom oxide (of ONO) and become stored in the charge storage medium. This injection of electrons into the charge storage medium increases the threshold voltage of the memory cell. The threshold voltage (Vt) of the memory cell can later be measured, or “read”.
The NROM cell can store charges in two separate (sometimes referred to as “left” and “right”) bit storage regions 321 and 323 of the charge-trapping layer 324. Depending on which bit (storage region) is desired to be programmed, the left and right diffusion regions 314 and 316 can act as source and drain, or as drain and source. The left and right bit storage areas are generally above and adjacent to the respective left and right diffusion regions (or “junctions”). The gate always functions as the gate.
It is important to manage the injection of electrons in an NROM cell, so that (for example) when programming the right bit, most of the electrons are injected into the right bit storage region (and conversely, when programming the left bit, most of the electrons are injected into the left bit storage region). Else, there can be effects resulting from “far from junction” electrons, discussed hereinbelow. With CHE programming, the situation is generally well characterized (under control).
A byproduct of CHE injection of electrons in NVM memory cells can be what is called “secondary injection”, or “secondary electron injection”, and may be abbreviated “SEI”.
Generally, the “primary” channel electrons (e1), as they accelerate from source to drain, impact valence electrons in the channel, next to the drain, ionizing valence elections in the substrate, and resulting in the generation (creation) of electron/hole pairs (e2/h2). The generated electrons e2 may be collected by the drain. However, the generated holes h2 may accelerate towards the low substrate potential Vb of the substrate, back under the channel region. Within the substrate, another impact ionization may occur, this time between holes h2 and valence electrons, creating another electron/hole pair e3/h3. Holes h3 are pulled further into substrate, and are generally of no concern. However, electrons e3, called secondary electrons, may be accelerated towards the positive gate potential Vg of the gate and, if they have gained sufficient energy, they can be injected into the charge storage medium.
The generation and injection of secondary electrons can be of great benefit to a floating gate memory cell, but generally causes problems for an NROM memory cell, because it has proven itself to be difficult to control—electrons injected far from the junction cause problems with reading, and retention.
The phenomenon of the generation of secondary electrons and problems associated with their injection into the charge storage areas (see 321, 323, FIG. 3) of NROM memory cells has been well recognized. The following commonly-owned patents are specifically referenced:                U.S. Pat. No. 6,429,063 (filed Mar. 6, 2000), entitled NROM Cell With Generally Decoupled Primary and Secondary Injection (hereinafter referred to as the '063 patent), and        U.S. Pat. No. 6,583,007 (filed Dec. 20, 2001), entitled Reducing Secondary Injection Effects (hereinafter referred to as the '007 patent).        
The '063 patent, for example, discloses techniques for decoupling injection of channel hot electrons into a charge trapping layer of an NROM cell from injection of non-channel (secondary) elections into the charge trapping layer, as well as for minimizing the generation of the non-channel (secondary) electrons. As disclosed therein, secondary injection reduces the performance of NROM cells because secondary electrons are injected far from the bit line junctions. These secondary electrons are not removable during erasure and thus, reduce the ability of the NROM cell to separate between the two charge storage areas.
The '007 patent, for example, discloses methods and apparatus for managing and reducing effects of secondary injection in non-volatile memory (NVM) devices that have a non-conducting charge trapping layer, such as NROM devices, and also discloses methods and apparatus for preventing punch-through voltages from detrimentally affecting erase operations in the NVM device that has a non-conducting charge trapping layer.
The problem of far from junction injection can occur with both CHE injection and secondary injection of electons, and boils down to non-localization of charge in the ONO nitride layer (324).
The solutions set forth in the '063 and '007 patents are exemplary of techniques for trying to control the injection point of secondary and hot electron injection. However, the charge location is difficult to control since the injection of hot and secondary electrons can have a wide distribution (“wide” equates with “far from junction”).
Another, what one might deem “obvious” solution, is to physically separate the nitride charge storage layer (324) into two pieces, strips, or stripes. Such a physical solution, of course, involves elaborate processing steps to accomplish and, if it takes up more space, may tend to be self-defeating (generally speaking, there would be limited benefit to making a memory cell perform better, if it needs to be larger).
A technique for decreasing charge distribution and diffusion during and after CHE injection is discussed in Scalable 2-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory with physically separated local nitrides under a merged gate, Lee et al., (Samsung), Solid State Electronics 48 (2004), pp 1771-1775, incorporated by reference in its entirety herein. Generally, the nitride layer (the whole ONO stack) is formed in two distinct sections (may be referred to as “strips”, or “stripes”), rather than as one single planar structure, under the gate. Although the “brute force” approach discussed in the article may provide good 2 bit separation (for either CHE or SEI), it is a complicated process which may result in a non-uniform (thickness and characteristics) ONO stack.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at “Non Volatile Memory Technology”, 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety.